1. Field of the Invention
The invention relates to a semiconductor device, particularly to a semiconductor device provided with a delay locked loop (DLL) for phasing a signal inputted to or a signal outputted from the semiconductor device.
2. Description of the Related Art
There is a semiconductor device provided with a DLL circuit for phasing an input signal inputted from an outside of a semiconductor device, for example, an input clocked signal with an output signal which is outputted to the outside of the semiconductor device, for example, an output clock signal. The DLL circuit is provided with an internal delay reproduction circuit. The internal delay reproduction circuit reproduces delay time (hereinafter referred to as internal delay time) that is the sum of a delay time of a signal taken for inputting to the DLL circuit through an input pin via a pad or a buffer and a delay time of a signal taken for outputting from the DLL circuit through an output pin via the buffer or the pad. The internal delay time reproduced by the internal delay reproduction circuit is generally adjusted in advance by a metal option.
Since there occurs dispersion in process such as difference between rods and devices in mass production of semiconductor devices, there occurs the necessity to readjust the internal delay reproducing circuit. However, since the internal delay reproducing circuit is adjusted by a metal option in a conventional semiconductor device, it is very difficult to adjust or evaluate the internal delay reproducing circuit.